features s1202 block diagram general description nile sts-12 atm/ds3 sonet mapper part number s1202 revision 3.8 - may 2000 amcc summary datasheet production information - the information contained in this document is about a product in its fully tested and character- ized phase. all features described herein are supported. con- tact amcc for updates to this document and the latest product status. ? processes valid combinations of sonet/sdh sts-12c/au-4-4c, sts-3c/au-4, or sts-1 tributaries within an sts-12/stm-4. terminates and generates sonet/sdh section, line, and path layers. provides ds3 mapping and demapping for 12 sts-1s and supports clear channel ds3. supports atm payload mapping into sts-12c/au-4-4c & sts-3c/au-4, as well as direct atm or atm plcp for ds3 tributaries. supports m23 and c-bit parity clear channel ds3 map- ping, as well as clear channel ds3 transparent passthrough mode. provides a 77.76 mhz 8-bit bus interface on the sonet/sdh side in both the tx and rx directions. provides a 50 mhz 16-bit utopia lvl 2 interface on the sys- tem side in both the tx and rx directions. programmable utopia addresses to support multi-phy operation. generic 8-bit microprocessor interface for configuration and status monitoring. supports ieee 1149.1 jtag testing. packaged in a 388 pin bga. implemented in 3.3v with 5v tolerant i/o. loopback capability for sonet/sdh, ds3 and atm. the s1202 is a highly integrated chip that implements sonet/sdh processing and atm mapping functions for sts-12/stm-4 data streams. in addition, it supports ds3 tributaries, in an sts-1 spe, with provisionable support for m23 or c-bit parity oh, as well as clear channel pass-through, direct mapping of atm cells, or atm plcp mapping. the s1202 is sonet and sdh standards compli- ant with bellcore gr-253 and ansi t1.105, and itu g.707, respectively. the s1202 is also ds3 standards compliant with bellcore gr-499 and ansi t1.107-1995 and atm stan- dards compliant with utopia specification level 2. the s1202 supports full-duplex processing of sonet/sdh data streams with section, line, & path overhead processing. the device supports framing, scrambling/descrambling, alarm signal insertion/detection, and bit interleaved parity (b1/b2/b3) processing. serial interfaces for e1, e2, f1 and line and section dcc are also provided. a general purpose 8-bit microprocessor interface is provided for device initialization, control, and monitoring. the interface supports both intel and motorola type microprocessors, and is capable of operating in either an interrupt driven or polled-mode configuration. applications atm switches packet over sonet routers and switches sonet/sdh add drop multiplexers, terminal multiplexers and digital cross connects test equipment tx_atm_dat[15:0] pointer interpret poh monitor toh drop toh monitor rx framer line side interface tx framer toh insert spe/vc generate tx_sdcc_data tx_sdcc_clk tx_ldcc_data tx_ldcc_clk tx_e1e2f1_clk rx_sdcc_data rx_sdcc_clk rx_ldcc_data rx_ldcc_clk rx_e1e2f1_clk rx_e1e2f1_data d[7:0] addr[11:0] csn rdb(dsb) wrb(rwb) rdyb(dtackb) busmode intb microprocessor i/f jtag port gpio reg tdi tck tms trtsb gppio[15:0] tx_data[7:0] tx_clk78 tx_frame_in rx_data[7:0] rx_clk78 rx_frame_out tx_8k_clk rx_extlos rx_lais_out rx_lof_out rx_oof_out rstb aps_intb ts_en tx_e1e2f1_data 1 12 ds3 1 12 ds3 fr prbs det fr prbs gen dl insert tx_dl_data tx_dl_enb dl drop rx_dl_data rx_dl_enb febe tx_ds3[1:4][1:3]data rx_ds3[1:4][1:3]fifo[1:0] 1 12 ds3 dmap 1 12 ds3 map 1 12 plcp 1 12 1 12 atm 1 12 atm proc proc proc plcp proc tdo clear channel ds3 clear channel ds3 tx_prty tx_soc tx_clk tx_enb tx_adr[4:0] tx_clav[3:0] rx_atm_dat[15:0] rx_prty rx_soc rx_clk rx_enb rx_adr[4:0] rx_clav[3:0] rx_ds3[1:4][1:3]data rx_ds3_x_y_gap_clk tx_frame_out rx_frame_in tx_ds3[1:4][1:3]clk rx_ds3_x_y_clk dl_clk dl_sync tx_ds3[1:4][1:3]fifo tx_ds3[1:4][1:3]x1_in rx_ds3[1:4][1:3]x1_out 1 12 tx fifo 1 12 rx fifo rx utopia i/f utopia tx i/f
200 brickstone square, andover, ma 01810 ph: 978/623-0009 fax:978/623-0024 amcc s1202 sts-12 atm/ds3 sonet mapper revision 3.8 - may 2000 summary datasheet overview and applications sonet processing the s1202 implements sonet/sdh processing and atm mapping functions for sts-12/stm-4 data streams. it can support any combination of sts-12c, sts-3c, or sts-1 sig- nals within an sts-12, or any combination of au-4-4c or au-4 signals within an stm-4. in addition, it can support ds3 tributaries, in sonet, with provisionable support for clear channel passthrough, direct mapping of atm cells, or atm plcp mapping. a toh/soh interface provides direct add/drop capability for e1, e2, f1, and both section and line dcc channels. on the transmit side the s1202 generates section, line, & path overhead. it performs framing pattern insertion (a1, a2), scrambling, alarm signal insertion, and generates section, line and path bit interleaved parity (b1/b2/b3) for far-end performance monitoring. on the receive side the s1202 processes section, line, & path overhead. it performs payload framing (a1, a2), descram- bling, alarm detection, bit interleaved parity monitoring (b1/b2/b3), and error count accumulation for performance monitoring. atm processing when configured for atm cell processing, the s1202 transmit atm processor will perform all necessary cell encapsulation including hec generation, cell level scrambling (x 43 +1), and idle cell insertion to adapt the cell rate to the spe. when receiving data from the line side, it performs cell delineation, rx header control, descrambling, and receive cell rate adap- tation. ds3 processing the s1202 provides ds3 mapper and de-mapper functions. the ds3 mapper accepts data from an external ds3 input, from looped-back ds3 tributaries, or from internal ds3 frame generators. the internal ds3 frame generators are used for atm, plcp, or prbs data. the s1202 maps the data into sts-1 sonet payloads. the s1202 ds3 de-mapper support includes the ability to extracts ds3 or atm data from the sonet signal. ds3 sig- nals can contain atm, plcp, or clear channel ds3 data. for atm or plcp data, the s1202 frames on the ds3 and extracts these signals from the ds3 payload. for clear chan- nel ds3 data, the s1202 generates rx serial (nrz) data sig- nals smoothed to match a ds3 clock input that is provided to the device, as well as a fifo fill indication, provided for phase lock loop adjustment. the s1202 also provides full ds3 framing, monitoring, and extraction for full ds3 support. line-side interface on the line-side, the s1202 supports an 8-bit parallel inter- face which operates at 77.76 mhz. the device is typically connected to a parallel-to-serial converter, which is in turn connected to an electrical-to-optical converter for interfacing to the fiber optic interface. (see figure below.) system interface the s1202 supports a utopia level 2 interface, operating at 50 mb/s, for providing atm cell transfers to/from the system interface. the s1202 also supports up to 12 ds3 tributaries. for clear channel ds3 data, the s1202 generates rx serial (nrz) data signals smoothed to match a ds3 clock input that is provided to the device, as well as a fifo fill indication, provided for phase lock loop adjustment. tx_data[7:0] tx_clk78 rx_clk78 rx_data[7:0] p/s & s/p sonet xcvr with clk recovery serrxd sertxd microprocessor control control amcc s3032 sumitomo sdm7202 hp hfct5208 reference clock fiber optic transceiver sonet line side interface rx_los s1202 amcc addr data 8 12 tx_clk tx_sys_dat[15:0] rx_clk rx_sys_dat[15:0] utopia level-2 system interface toh insertion and extraction atm switch or u t o p i a ds3 ds3 clear channel for tx_ds3_[1:12]_data rx_ds3_[1:12]_data rx_ds3_[1:12]_gap/sm_clk rx_ds3_[1:12]_fifo_[1:0] tx_ds3_[1:12]_clk packet over sonet application multi channel hdlc processor ip router switching/ routing logic channelized 622 mb/s atm application typical applications
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